ESP32/ESP8266

The ESP32 is a series of low-cost, low-power, single-chip microcontrollers with integrated Wi-Fi and dual-mode Bluetooth. The ESP32 family uses the Tensilica Xtensa LX6 microprocessor and includes dual-core and single-core variants with built-in antenna switches, RF converters, power amplifiers, low-noise receiver amplifiers, filters and power management modules.

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processor:
CPU: Xtensa dual core (or macro core) 32-bit LX6 microprocessor, working clock 160/240 MHz, computing power up to 600 DMIPS


Storage:
448 KB ROM (64KB+384KB)
520 KB SRAM
16 KB RTC SRAM, SRAM is divided into two types
The first part, 8 KB RTC SRAM is a slow memory, which can be accessed by the secondary processor in Deep-sleep mode
The second part, 8 KB RTC SRAM is a fast memory, which can be used for data storage and accessed by the main CPU during RTC startup in Deep-sleep mode.
1 Kbit eFuse, of which 256 bits are dedicated to the system (MAC address and chip settings); the remaining 768 bits are reserved for user applications, which include Flash encryption and chip ID.
QSPI supports multiple flash/SRAM
SPI memory can be used to map to external memory space, part of the memory can be used as external memory Cache
Maximum support 16 MB external SPI Flash
Maximum support 8 MB external SPI SRAM


Wireless transmission:
Wi-Fi: 802.11 b/g/n
Bluetooth: v4.2 BR/EDR/BLE


External interface:
34 GPIO
12-bit SAR ADC, up to 18 channels
2 8-bit D/A converters
10 touch sensors
4 SPI
2 I2S
2 I2C
3 UART
1 Host SD/eMMC/SDIO
1 Slave SDIO/SPI
Ethernet interface with dedicated DMA, support IEEE 1588
CAN 2.0
Infrared transmission
Motor PWM
LED PWM, up to 16 channels
Hall sensor


Address space:
Symmetric addressing mapping
Data bus and command bus can be addressed to 4GB (32bit) respectively
1296 KB on-chip access addressing
19704 KB external access addressing
512 KB external address space
Part of the memory can be accessed by the data bus or the command bus
Security Mechanism


Safe boot:
Flash ROM encryption
1024 bit OTP, users can use up to 768 bit
Hardware encryption accelerator